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Eli Hughes (VP of Research and Development, TZero Labs)
Date: Thursday, April 19
Time: 9:00am - 11:00am
Pass type: Conference (Paid) - Get your pass now!
Conference Track: Embedded Hardware Design & Verification, Embedded Software Design & Verification
Vault Recording: TBD
Audience Level: N/A
Designing for operation in space is challenging. It is even more challenging when you want to push on the boundaries of what is possible on a small budget. In this session we will investigate the process of transitioning an imaging processing algorithm for X-ray astronomy from a low-resolution "software" approach to a high data rate, high-resolution "hardware"-based approach using an FPGA to achieve a higher NASA technology readiness level (TRL).
During the session with will look at both the processing algorithm, the approach to implementation, and the verification strategy. Along the way, will dive into the design of "Mr. X," which was the hardware platform used for implementing the processing algorithm. Mr. X is a 20-layer PCB that incorporates a Xilinx Virtex 5 FPGA, four channels of QDR-II SRAM, and a Cortex M0 microcontroller, all of which have radiation-hardened equivalents. We will discuss the challenges of the hardware design to be able to meet schedule, budget, risk, and performance targets.
Attendees will see the process of developing an embedded imaging processing concept that will be targeting a space application using a FPGA. They will see both a processing architecture for high speed X-ray event detection and the hardware design needed to test and verify the algorithm. They will also gain an appreciation for the challenges an engineer may face when designing for space environments.